1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that has a function of detecting a defective memory cell or the like which lacks a capability to cope with the requirement for a write recovery time, in connection with the process of performing a screening test.
2. Description of the Prior Art
FIG. 5 is a block diagram showing the configuration of a conventional semiconductor memory device. In FIG. 5, an internal clock generating circuit 1 is a circuit which generates a synchronizing internal clock based on an input external clock CLK, a command decoder 2 is a decoder which decodes a command based on data input to input terminals /RAS, /CAS, /WE and /CS, and an internal address generating circuit 3 is a circuit which generates an internal address for row address and column address of a memory cell array 4 based on address data input to an ADD terminal. The memory cell array 4 has a plurality of memory cells arranged in a matrix form.
Moreover, a row system control signal generating circuit 5 is a control circuit that controls the selection of a word line of the memory cell array 4. In the row system control signal generating circuit 5 there is formed a circuit consisting of a delay circuit 6a, a NAND circuit 6b and an inverter circuit 6c, as shown in FIG. 6. This circuit sets the selection timing of a word line and the nonselection timing of a word line. A row decoder 6 is a circuit that decodes the row address of the memory cell array 4, and a column decoder 7 is a circuit that decodes the column address of the memory cell array 4.
A sense amplifier circuit 8 is an amplifier circuit which amplifies a signal read from the memory cell array 4, a data amplifier circuit 9 is an amplifier circuit which further amplifies the output signal of the sense amplifier circuit 8 to the CMOS level, and a column system circuit 10 is a control circuit which controls a column selection line. The column system circuit 10 controls the decision as to the rise and fall timings, or the like of the column selection line of the column decoder 7. An input and output circuit 11 is a circuit which controls data input to and data output from a terminal DQ.
Next, referring to the timing chart in FIG. 7, the operation of the conventional device in FIG. 5 will be described. FIG. 7(a) and FIG. 7(b) show an external clock CLK and a command decoded by the command decoder 2, respectively. First, assume that data RASB, CASB, WEB and CSB input to the input terminals of the command decoder 2 at the rise of cycle C1 of the clock CLK are decoded to be an active command as shown in FIG. 7(b). An active command is a command that selects the word line corresponding to a row address input from the outside.
When the device goes to the active command state, a signal RAS2B output from the command decoder 2 to the row system control signal generating circuit 5 falls to a low level as shown in FIG. 7(c). Subsequently to that, a signal RAS3B output from the row system control signal generating circuit 5 to the column decoder 6 falls to a low level as shown in FIG. 7(d). In the meantime, in the internal address generating circuit 3, a row address is generated based on the data input when the device was at the active command, and the address is supplied to the row decoder 6.
In the row decoder 6, the word line corresponding to the input row address is brought to a high level as shown in FIG. 7(e) to select the word line corresponding to the row address. When the word line is selected, data in the memory cell 4 connected to the word line are read at the sense amplifier circuit 8 via a bit line pair as shown in FIG. 7(f), and the data are amplified by the sense amplifier circuit 8.
Then, if it is assumed that the result of decoding of the input data at the rise of cycle C2 of the external clock CLK is a write command as shown in FIG. 7(a), a column selection line 1, corresponding to the column address input then from the internal address generating circuit 3 to the column decoder 7, is selected as shown in FIG. 7(g), and the column selection line 1 is kept at the high level for a prescribed duration. With the selection of the column selection line 1, data input to the DQ terminal at the input of the write command are supplied to the sense amplifier circuit 8 via the input and output circuit 11 and the data amplifier circuit 9 to be written to the sense amplifier in the sense amplifier circuit 8 selected by the column selection line 1. The written data (FIG. 7(f)) are supplied at the same time to the memory cell array 4 via the bit line pair to be written to the memory cell that has been selected by the word line.
Next, if it is assumed that the result of decoding of the input data at the rise of cycle C3 of the external clock CLK is a write command again as shown in FIG. 7(a), a column selection line 2 corresponding to a column address input then from the internal address generating circuit 3 is selected (at the high level) for a prescribed duration by the column decoder 7 as shown in FIG. 7(i). With the selection of the column selection line 2, data input to the DQ terminal at the input of the write command are supplied to the sense amplifier circuit 8 via the input and output circuit 11 and the data amplifier circuit 9 to be written to the sense amplifier selected by the column selection line 2 in the sense amplifier circuit 8.
The written data (FIG. 7(h)) are supplied at the same time to the memory cell array 4 through the bit line pair to be written to the memory cell that has been selected by the wordline. Here, the time during which the column selection lines 1 and 2 are kept at the high level, namely, the write time to the sense amplifier circuit 8 is set in advance.
Next, if it is assumed that the result of decoding of the input data at the rise of cycle C4 of the external clock CLK is a precharge command as shown in FIG. 7(a), the signal RAS2B of the command decoder 2 rises to the high level as shown in FIG. 7(c). Subsequently to that, the signal RAS3B from the row system control signal generating circuit 5 rises to the high level as shown in FIG. 7(d), and in response to this the word line that has been selected goes to the unselected state (at the low level) as shown in FIG. 7(e). Here, in the semiconductor memory device in FIG. 5, the time during which the column selection line stays at the high level, namely, the write time to the sense amplifier circuit 8 is set in advance such that the level falls off after the lapse of a prescribed time from the time of its rise.
Besides the above, there has also been known a conventional device in which the high level duration of the column selection line, namely, the write time to the sense amplifier circuit 8, is set in synchronism with the external clock CLK. FIG. 8 is a timing chart showing the operation of such a semiconductor memory device. FIG. 8(a) to FIG. 8(i) correspond to FIG. 7(a) to FIG. 7(i), respectively. In this case, the only difference of FIG. 8 from FIG. 7 is the duration of the high level of the column selection lines shown in FIG. 8(g) and FIG. 8(i), and the rest is the same as in FIG. 7. In this conventional example, the high level duration of the column selection lines, namely, the write time to the sense amplifier circuit, agrees approximately with the cycle of the external clock CLK. In either of FIG. 7 and FIG. 8, the write time to the memory cell from the sense amplifier circuit to the memory cell via the bit line pair depends on the cycle time tCK of the clock.
Now, in the conventional semiconductor memory devices, there are some whose sense amplifier or memory cell needs longer write time than others due to defect of one kind or another, and such a defective sense amplifier and a defective memory cell are required to be rejected by a screening test prior to the shipping. Moreover, the minimum time from the input of a write command to the input of a precharge command is regulated by a specification called tDPL (write recovery time), and sense amplifiers and memory cells that fail to have a margin to tDPL are required to be rejected as defective products.
As a method of detecting a defective sense amplifier or a defective memory cell that lacks the capability to cope with the requirement for tDPL, one may consider, for example, a test in which the value of tDPL is made smaller than the standard value. Since, however, the cycle time (tCK) of the external clock will have to be reduced at the same time, it was not possible to discriminate which of tCK and tDPL was the true cause of the defect.
Objects of the Invention
It is the object of the present invention to provide a semiconductor memory device that makes it possible to detect simply and accurately a defective sense amplifier or a defective memory cell generated due to the small value of tDPL.
Summary of the Invention
The semiconductor memory device according to the present invention comprises a memory cell array having a plurality of bit lines, a plurality of word lines provided perpendicular to the plurality of bit lines, and a plurality of memory cells disposed at the intersections of the word lines and the bit lines, a row decoder which selects a prescribed word line out of the plurality of word lines in response to a row address when the control signal is in an activated state and puts all the word lines to an unselected state when the control signal is in an inactivated state, a test mode decision circuit which decides a test mode and generates a test signal, and a control signal generating circuit which brings the control signal to the activated state for a prescribed duration in response to an instruction signal, where the control signal generating circuit has a means which, in response to the occurrence of a test signal, hastens the change of the control signal to the inactivated state sooner than in the normal operation.